6.1 Introduction

In the first part of this exercise, we present the details of two components that work together to evaluate a series of simple linear matrix operations. One component serves as the driver, while the other provides the LinearOp port. The specification of this port is found in the file $TUTORIAL_SRC/ports/sidl/arrayop.LinearOp.sidl, partially reproduced here for easy reference

  
   ...
   
 /** This port can be used to evaluate a matrix operation of the form
   * of the form
   *  R = Sum[i=1, N] {Alpha_i A_i v_i} + Sum[j=1, N] {Beta_j v_j}
   * Where:
   *    alpha_i, Beta_j   Double scalar
   *    A_i               Double array of size [m, n]
   *    v_i, v_j          Vector of size [n]
   *    A_i  v_j          Matrix vector multiplication
   */
      interface LinearOp extends gov.cca.Port 
      {
 /** Initialize (or Re-Initialize) internal state in preparation
   * for accumulation.
   */
         void  init();
   
 /** Evaluate Acc = Acc + alpha A x,  where
   *   Acc     The internal accumulator maintained by implementors 
   *           of this interface
   * return the result  in vector y (of size m)
   */
         int mulMatVec (in double               alpha, 
                        in rarray<double, 2>    A(m, n), 
                        in rarray<double, 1>    x(n), 
                        inout rarray<double, 1> y(m),
                        in int                  m,
                        in int                  n);
            
 /** Evaluate Acc = Acc + beta v,  where
   *   Acc     The internal accumulator maintained by implementors 
   *           of this interface
   * return the result  in vector y (of size m)
   */
         int addVec ( in double            beta,
                      in array<double, 1>  v,  
                      out array<double, 1> r);
                  
 /** Get result of linear operators
   *
         int getResult (inout rarray<double, 1>  r(m),
                        in    int                  m);
                  
      }
      
   ...

Note The port methods mulMatVec and getResult use SIDL raw arrays (also referred to as r-arrays), which are designed to simplify implementation in Fortran dialects (especially Fortran77). Raw arrays are assumed to adhere to column-major memory layout, with zero-based indexing. Further details of raw SIDL arrays are in the Babel User Guide . The port method addVec uses the `normal' SIDL array class. This class allows access to arrays through accessor functions. There are also provisions that allow access to the underlying array memory for more efficient operations. Refer to the Babel User Guide for more details on normal SIDL arrays.

The tutorial source contains fully implemented three components that provide the LinearOp port. The components F90ArrayOp, F77ArrayOp, and CArrayOp are in $TUTORIAL_SRC/components/, in the directories arrayOps.F90ArrayOp, arrayOps.F77ArrayOp, and arrayOps.CArrayOp, respectively. In addition, a driver component that uses the LinearOp port is in $TUTORIAL_SRC/components/arrayDrivers.CDriver/.

In the following sections, we will present some of the aspects of using SIDL arrays, using the code in the driver and the three arrayOps components as examples. You will then be asked to implement a component that provides a NonLinearOp port and a driver, using the aforementioned four components as a template.